Generally, a system-on-chip (SoC) design must include an embedded processor core, memory and a sufficient number of peripheral devices so that the embedded processor may perform most of its functions without leaving the chip. In the past this required sophisticated proprietary bus architectures to connect the various devices together. Other more traditional bus architectures, for example, multi-master bus architectures with bi-directional busses are individually designed for the specific system algorithm or application specific integrated circuit (ASIC). However, such bus architectures do not support concurrency and as such a subsequent transaction or transfer must wait for an existing transaction or transfer to complete.
While many systems handle concurrency, there is still a need for improvements. For example, International Application published under the Patent Cooperation Treaty, Publication Number WO 01/35210 describes a bus architecture method for a communication processor. While the bus architecture disclosed in WO 01/35210 supports non blocking or concurrency operations, the system uses a shared bus arbitration scheme or a centralized arbitration scheme. Such system designs desire improvements in order to increase scalability. The WO 01/35210 application in most likelihood also uses a centralized address decoding scheme that also desires improvements.